The fabrication process of VLSI components includes a large number of manufacturing steps wherein effects are created leading to circuit malfunction and low performance. By detecting manufacturing defects as well as characterizing the semiconductor devices performance, test equipment plays an important role that enables semiconductor manufacturers and designers to improve the manufacturing yield in addition to enhancing the quality and reliability of the end products.
Numerous electrical test methods have been put in place to monitor the quality and integrity of the IC fabrication process. Probing a wafer is typically the first time that chips are tested to determine if they function as they are designed to do. A tester probe card combination must provide a stable deterministic electrical behavior throughout the entire wafer testing process. Any variability of the test measurement tool, whether tester or probe card induced typically, reduces the repeatability and accuracy of the measurements being made.
The conventional approach to wafer test for ensuring test probing reliability includes:                a) A computer controlled tester performing a continuity test before bringing the probes on a wafer. The tester lands probing tips on a metal plate preferably made of cooper or tungsten, and a check is performed to determine whether every probe makes contact with the metal plate. Depending on the probing pressure setting and the landing topography difference from the metal plate to a macro in the chip limits the test to only a sanity check. A slight bending or soiled tip may be the cause of differences from other probes which may produce an impact on further device measurements that can no longer be detected from this test.        b) A test technician aligning the probing tips on the designated probing pads on wafer at a predetermined site. Then technician needs to check for any probe marks on the landing pads before setting the tester to run in an automatic mode. Depending on the training, experience and working attitude, generally this process does not ensure a reliable procedure to set up a test. For instance, a bent probe may barely land on the edge of a metal pad while others may ‘drill’ the center of the pads. Moreover, a bent probing tip may step away or even outside the landing pad of a second or subsequent wafers to be tested, even in the absence of a system warning.        c) Performing a continuity check prior to probing the wafer or chip. Before initiating a device measurement, the tester is set to run a continuity check when probing a macro at various sites on the wafer. A specification range is provided to evaluate the mean value of the measured current and deciding whether the probe makes contact with the test pads. At this stage, after the tester has been set to run automatically, it may continue collecting data while testing macros test in a lot, along with the probe continuity check. Then, a disposition form informs the technician when retesting the wafers is necessary after all the tests have been completed.        
The above described methods fail to offer a reliable process that ensures the required high quality probing necessary for the next generation of testing wafers, and do not identify nor offer a finer resolution on the probe commonality. By way of example, a soiled probing tip typically introduces a higher contact resistance which impacts the device measurement results and which if ignored, mislead the test engineer into making a wrong decision.
Due to inherent tester specifications (including drift resolution, repeatability, linearity) with the added accumulation of probe contact resistance (Cres), it is not realistic to assume that the tester/probe card combination becomes deterministic over time.
Referring to FIG. 1a, there is shown is a schematic diagram showing a prior art test setup to perform a continuity test, the test setup consisting of a plurality of pads of a DUT, an array of probes and a plurality of resistive connectors.
FIG. 1a shows an array of probing tips that is aligned to make contact to a plurality of probing pads. The probe continuity test is set up to take current measurements by applying a constant voltage to each probe, from p1 to p(n−1) while grounding the end probe Pn—ground. Pn—ground is intended to collect current sequentially for each probe to which the voltage is applied.
Referring to FIG. 1b, there is shown a schematic diagram of an alternate prior art test setup to perform the continuity test illustrated in FIG. 1a. Shown therein is a plurality of probing tips contacting landing pads. It is assumed that one probing tip, e.g., p2 does not make good contact to its corresponding landing pad, perhaps because the landing contact is not as clean as it should be. The resistance of the path from the probe (p#) to which the voltage is applied to the probe pn—ground, where current is measured, is represented by CR#+(n−#)*R, where CR# represents the contact resistance of the probing tip and its landing pad; n, is the total number of probes in the probe card; #, is the probing tip number; and R, the resistance between each neighboring landing pad.
Illustrated in the FIG. 1b is a slight bent or soiled tip, p2, making an imperfect contact with the probing pad. In this case, it does not cause an open contact or fail the continuity test. However, an additional contact resistance ΔR is introduced between probe p2 and probe Pn—ground.
FIG. 1c illustrates the normalized measurement data distribution of each individual probe making contact with the pads.
After taking multiple measurements, the distribution of continuity current data is generated. The collected current data can be converted and normalized to the corresponding contact resistance of the probing tip and landing pad, which can be presented by CR#=(V/I#)−(n−#) R, where # is the probing tip number; n, the total number of the probes in the probe card; R, the resistance between each neighboring landing pad; V, the applied voltage to the probe number #; and I, the measured current from the end probe pn—ground. It is assumed that the conducting wires between each neighboring pads has the same resistance as in an ideal condition.
The solid arrow represents the mean of the distribution. In an ideal case, the mean of each probe distribution should be the same. However, the distribution of the probe may shift ΔR due to a slight bending or soiled tip (illustrated by a dotted line). The shift of ΔR may not cause a continuity test fail; yet, it may cause a significant impact on the transistor's performance characterization.
In a conventional probe check, the setup described in FIG. 1a permits only the continuity current measurement to be taken between each probe and the end probe or between each pair of neighboring probes. A continuity current specification range or a contact resistance specification range is provided to decide if any probe has an open contact to the landing pad. Data may or may not be normalized in the conventional process. By way of example, still referring to FIGS. 1b and 1c, probe degradation, as illustrated by probe p2, cannot be detected by conventional methods. The test generates unreliable device data that may have a significant impact on the engineering time spent for device characterization, and on the quality of the end product.
Therefore, there is a need to provide a system and a method for statistically measuring the tester probe cards' “noise floor” which is essential to understand the process variability for a given advanced semiconductor technology.